CWE-1422: Exposure of Sensitive Information caused by Incorrect Data Forwarding during Transient Execution

Common consequences

• Confidentiality

  Read Memory

Potential mitigations

• Architecture and DesignEffectiveness: Limited

  The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.

• RequirementsEffectiveness: Defense in Depth

  Processor designers, system software vendors, or other agents may choose to restrict the ability of unprivileged software to access to high-resolution timers that are commonly used to monitor covert channels.

• RequirementsEffectiveness: Moderate

  Processor designers may expose instructions or other architectural features that allow software to mitigate the effects of transient execution, but without disabling predictors. These features may also help to limit opportunities for data exposure.

• RequirementsEffectiveness: Limited

  Processor designers may expose registers (for example, control registers or model-specific registers) that allow privileged and/or user software to disable specific predictors or other hardware features that can cause confidential data to be exposed during transient execution.

• Build and CompilationEffectiveness: Incidental

  Use software techniques (including the use of serialization instructions) that are intended to reduce the number of instructions that can be executed transiently after a processor event or misprediction.

• Build and CompilationEffectiveness: High

  Isolate sandboxes or managed runtimes in separate address spaces (separate processes).

• Build and CompilationEffectiveness: Moderate

  Include serialization instructions (for example, LFENCE) that prevent processor events or mis-predictions prior to the serialization instruction from causing transient execution after the serialization instruction. For some weaknesses, a serialization instruction can also prevent a processor event or a mis-prediction from occurring after the serialization instruction (for example, CVE-2018-3639 can allow a processor to predict that a load will not depend on an older store; a serialization instruction between the store and the load may allow the store to update memory and prevent the...

• Build and CompilationEffectiveness: Limited

  Use software techniques that can mitigate the consequences of transient execution. For example, address masking can be used in some circumstances to prevent out-of-bounds transient reads.

MITRE lists 2 more mitigations on the official entry.

Related weaknesses

CAPEC attack patterns that exploit it

CWE 4.20 links no CAPEC attack pattern to this weakness.