CWE-1191: On-Chip Debug and Test Interface With Improper Access Control
Description
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
- Abstraction
- BaseA weakness specific enough to point to detection and prevention methods.
- Likelihood of exploit
- Not rated by MITRE
- Status
- Stable
Common consequences
- Confidentiality
Read Application Data
- Confidentiality
Read Memory
- Authorization
Execute Unauthorized Code or Commands
- Integrity
Modify Memory
- Integrity
Modify Application Data
- Access Control
Bypass Protection Mechanism
Potential mitigations
- Architecture and DesignSeparation of PrivilegeEffectiveness: High
If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared when entering debug mode.